Quilt Packaging Reference Publications

Publications

Multiple articles and papers have been published on a variety of aspects of Quilt Packaging techology. Below is a list of peer-reviewed publications reporting on Quilt Packaging.

T. Ahmed, T. Lu, T.P. Butler, J.M. Kulick, G.H. Bernstein, A.J. Hoffman, D.C. Hall, S.S. Howard. “Mid-Infrared Waveguide Array Inter-Chip Coupling Using Optical Quilt Packaging.” IEEE Photonics Technology Letters ( Volume: 29, Issue: 9, May1, 1 2017 ), pp 755-758.

Abstract: “A MEMS-based mid-infrared (MIR) chip-to-chip optical coupling technique, optical quilt packaging (OQP), is described. Numerical simulations are performed to predict performance and establish fabrication tolerances. The OQP fabrication process is described in detail and MIR inter-chip optical coupling between two waveguide arrays joined by OQP is characterized. The coupling loss between Ge-on-Si passive MIR waveguides is found to be ~ 4.1 dB, which is the lowest butt-coupling loss reported between two chips.”
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P. Fay, G.H. Bernstein, T. Lu, J.M. Kulick. “Ultra-wide Bandwidth Inter-Chip Interconnects for Heterogeneous Millimeter-Wave and THz Circuits.” Journal of Infrared, Millimeter, and Terahertz Waves, September 2016, Volume 37, Issue 9, pp 874–880.

Abstract: “Heterogeneous chip-to-chip interconnects with low loss and ultra-wide bandwidths have been demonstrated. Coplanar waveguide-based interconnects between GaAs and Si die have been fabricated and characterized and the results compared to expectations from full-wave electromagnetic simulation. Broadband transmission characteristics were obtained, with insertion losses below 0.3 dB at 100 GHz and below 0.8 dB at frequencies up to 220 GHz demonstrated experimentally. The measured return loss exceeded 11.5 dB at all frequencies up to 220 GHz. The interconnects offer low latency, with a measured group delay of 0.69 ps. The measured results are in good agreement with full-wave simulations, indicating that the measured results do not suffer from significant impairments compared to theoretical predictions. The demonstrated interconnects offer an alternative to conventional approaches to millimeter-wave circuit and system integration, by enabling the compact realization of circuits in the microwave, millimeter-wave, sub-millimeter-wave, and THz frequency regimes in heterogeneous device technologies with very low chip-to-chip insertion loss.”
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T. Lu, J.M. Kulick, C. Ortega, G.H. Bernstein, S. Ardisson, R. Engelhardt, “Rapid SoC Prototyping Utilizing Quilt Packaging Technology for Modular Functional IC Block Partitioning.” Proceedings of 2016 International Symposium on Rapid System Prototyping (RSP) (Oct. 6-7, 2016).

Abstract: “A microchip integration technology called Quilt Packaging (QP) enables rapid prototyping of complex SoCs and microwave/RF systems, as well as optical, power, and DSP applications. QP is a direct edge-to-edge chip-level interconnect technology that can be implemented in a variety of materials and/or process technologies, and has been demonstrated in both planar and non-planar 3D architectures. Quilt Packaging technology can be applied to create a “Lego-like” design kit for ultra-fast prototyping and proof-of-concept chip-level system verification. Partitioning sub-components into small, inexpensive “chiplets” can allow for much faster design turns and greatly reduced first-pass prototype verification. In addition, QP enables low-loss, high-throughput chip-to-chip I/O interconnects while reducing size, weight, and power requirements, lessening the burden of design trade-offs for hardware system designers developing the next generation of microelectronic systems.”
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T. Lu, J.M. Kulick, J. Lannon, G.H. Bernstein, P. Fay. “Heterogeneous Microwave and Millimeter-wave System Integration Using Quilt Packaging.” Proceedings of 2016 IEEE MTT-S International Microwave Symposium (IMS) (May 22-27, 2016).

Abstract: “Quilt Packaging (QP) is a direct chip-to-chip edge-interconnect technology that offers extremely low interconnect loss and can be implemented on a variety of substrates. We report here the experimental demonstration of heterogeneous integration between Si and GaAs substrates. Ultrawide-bandwidth Quilt Packaging coplanar waveguide interconnects between Si and GaAs chips are presented along with preliminary thermal shock data. Fabricated structures on ~100 μm thick Si and GaAs chips exhibited chip-to-chip insertion losses below 0.5 dB up to 170 GHz, and below 1 dB up to 220 GHz from on-chip S-parameter measurements. Simulated results on a heterogeneous Si-GaAs quilted chipset on scaled QP interconnect exhibited chip-to-chip insertion losses below 0.5 dB up to 300 GHz, and below 1.5 dB up to 750 GHz. Despite the coefficient of thermal expansion mismatch between Si and GaAs, the interconnects also exhibited no adverse effects from thermal shock testing through 1250 cycles.”
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M.A.A. Khan, Q. Zheng, D. Kopp, W. Buckhanan, J.M. Kulick, P. Fay, A.M. Kriman, and G.H. Bernstein. “Thermal Cycling Study of Quilt Packaging.” Journal of Electronic Packaging J. Electron. Packag. 137, no. 2 (2015): 021008.

Abstract: “This paper describes studies of fatigue failure in QP, with attention to critical high-stress regions previously identified by finite-element modeling. Nodules were fabricated on silicon chips, and both single and quilted chips were thermally cycled up to 1000 times over a range of − 55 °C to 125 °C. Scanning electron microscopy (SEM) was used to detect mechanical failure. Focused-ion-beam cross-sectioning was used to expose the critical interior interfaces of QP structures for SEM examination. QP superconnects were found to be robust under all the test conditions evaluated.”
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K. Sparkman, J. LaVeigne, S. McHugh, J.M. Kulick, J. Lannon S. Goodman. “Scalable Emitter Array Development for Infrared Scene Projector Systems.” Proc. SPIE 9071, Infrared Imaging Systems: Design, Analysis, Modeling, and Testing XXV, 90711I (May 29, 2014).

Abstract: “Array sizes of 2048×2048 and larger are required to meet the high fidelity test needs of today’s modern infrared sensors. The Test Resource Management Center (TRMC) Test and Evaluation/Science and Technology (T and E/S and T) Program through the U.S. Army Program Executive Office for Simulation, Training and Instrumentations (PEO STRI) has contracted with SBIR and its partners to investigate integrating new technologies in order to achieve array sizes much larger than are available today. SBIR and its partners have undertaken several proof-of-concept experiments that provide the groundwork for producing a tiled emitter array. Herein we will report on the results of these experiments, including the demonstration of edge connections formed between different ICs with a gap of less than 10µm. “
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T. Ahmed, M.A.A. Khan, G. Vigil, J.M. Kulick, G.H. Bernstein, A.J. Hoffman, and S. Howard. “Optical Quilt Packaging: A New Chip-to-Chip Optical Coupling and Alignment Process for Modular Sensors.” Cleo: 2014, 2014.

Abstract: “A wide-bandwidth, highly efficient method of inter-chip waveguide coupling suitable for on-chip, mid-infrared sensing is discussed. Simulations and preliminary fabrication work on laser-to-waveguidecoupling are presented, with losses predicted to be better than 6 dB.”
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D.P. Kopp, M. A. A. Khan, G.H. Bernstein, and P. Fay. “Ultra-broadband Chip-to-chip Interconnects to 220 GHz for Si-based Millimeter-wave Systems.” IEEE International Interconnect Technology Conference, 2014.

Abstract: “Ultra-broadband chip-to-chip interconnects at high frequencies are demonstrated. These interconnects, based on the Quilt Packaging (QP) approach, appear to be promising for applications in millimeter-wave circuits due to their extremely wide bandwidth and ease of assembly. The performance of chip-to-chip interconnects in a 50 Ω coplanar waveguide environment on high-resistivity silicon substrates has been measured to 220 GHz using a vector network analyzer, and is compared with projections obtained from 3D electromagnetic modeling. Single-mode, resonance-free operation is demonstrated through 220 GHz, with insertion loss below 1.5 dB over the full frequency range. Although the resistance of the conductive epoxy (used for the prototypes reported here) limits the performance of the QP nodules, simulations indicate that better joining methods such as soldering promise to yield insertion loss of much less than 1 dB at 220 GHz.”
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Q. Zheng, D. Kopp, M.A.A. Khan, P.Fay, A.M. Kriman, and G.H. Bernstein. “Investigation of Quilt Packaging Interchip Interconnect With Solder Paste.” IEEE Transactions on Components, Packaging and Manufacturing Technology IEEE Trans. Compon., Packag. Manufact. Technol. 4, no. 3 (2014): 400-07.

Abstract: “We investigate mechanical, thermal, and microwave characteristics of the edge-interconnect scheme called quilt packaging (QP), using a pin transfer method for the application of solder paste. A novel pull test method for QP is introduced, and the pull strength for edge copper nodules is investigated. Thermal shock tests for QP interconnects with solder are performed. Pull strengths for QP interconnects before and after thermal shock are compared and failure mechanisms of QP are investigated. The simulation and experimental results show that QP provides ultrawidebandwidth, and the use of solder paste does not significantly affect the microwave performance of QP.”
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G.H. Bernstein, and J.M. Kulick. “Demonstration: Quilt Packaging for Heterogeneous Integration of CNN Systems.” 2014 14th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA), 2014.

Abstract: “A demonstration is presented at the 14th International Workshop on Cellular Nanoscale Networks and their Applications. The topic is the interchip interconnect technology known as Quilt Packaging™ (QP). QP offers many advantages for future, highly integrated CNN systems. The author will have demonstration materials on hand for inspection and discussion.”
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P. Fay, D. Kopp, T. Lu, D. Neal, G.H. Bernstein, J.M. Kulick, “Ultrawide Bandwidth Chip-to-Chip Interconnects for III-V MMICS, ” IEEE Microwaves and Wireless Components Letters, Vol. PP, Issue 99, November 2013.

Abstract: “Ultrawide bandwidth coplanar waveguide interconnects between GaAs chips based on a novel fabrication process are demonstrated. Fabricated structures on 100 μm thick GaAs chips exhibited chip-to-chip insertion losses below 1 dB up to 110 GHz, and below 2.2 dB up to 220 GHz from on-wafer S-parameter measurements. A return loss larger than 10 dB from 100 MHz to 220 GHz was measured. The measured responses are consistent with numerical simulations, including the effects of excess solder at the chip-to-chip interface. Numerical simulations indicate that further improvements in performance, with insertion losses as low as 1.1 dB at 220 GHz, should be possible by minimizing the excess solder.”
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T. Ahmed, T. Butler, A. Khan, J. M. Kulick, G. H. Bernstein, A. Hoffman and S. Howard, “FDTD modeling of chip-to-chip waveguide coupling via optical Quilt Packaging,” Proc. SPIE Optical System Alignment, Tolerancing and Verificaton VII, Vol. 8844, 2013.

Abstract: “We present Finite-Difference Time-Domain (FDTD) simulations to explore feasibility of chip-to-chip waveguide coupling via Optical Quilt Packaging (OQP). OQP is a newly proposed scheme for wide-bandwidth, highly-efficient waveguide coupling and is suitable for direct optical interconnect between semiconductor optical sources, optical waveguides, and detectors via waveguides. This approach leverages advances in quilt packaging (QP), an electronic packaging technique wherein contacts formed along the vertical faces are joined to form electrically-conductive and mechanically-stable chip-to-chip contacts. In OQP, waveguides of separate substrates are aligned with sub-micron accuracy by protruding lithographically-defined copper nodules on the side of a chip. With OQP, high efficiency chip-to-chip optical coupling can be achieved by aligning waveguides of separate chips with sub-micron accuracy and reducing chip-to-chip distance. We used MEEP (MIT Electromagnetic Equation Propagation) to investigate the feasibility of OQP by calculating the optical coupling loss between butt coupled waveguides. Transmission between a typical QCL ridge waveguide and a single-mode Ge-on-Si waveguide was calculated to exceed 65% when an interchip gap of 0.5 μm and to be no worse than 20% for a gap of less than 4 μm. These results compare favorably to conventional off-chip coupling. To further increase the coupling efficiency and reduce sensitivity to alignment, we used a horn-shaped Ge-on-Si waveguide and found a 13% increase in coupling efficiency when the horn is 1.5 times wider than the wavelength and 2 times longer than the wavelength. Also when the horizontal misalignment increases, coupling loss of the horn-shaped waveguide increases at a slower rate than a ridge waveguide.”
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M.A. Khan, J.M. Kulick, A.M. Kriman and G.H. Bernstein, “Design and Robustness of Quilt Packaging Superconnect,” Journal of Microelectronics and Electronic Packaging, Vol. 10, 8-14, 2013.

Abstract: “Quilt packaging (QP) is a novel high-speed super-connect (i.e., direct interchip interconnect), developed to improve electrical performance—signal delay, power loss, and so on. Ultrahigh bandwidth has already been demonstrated for QP, but its unique structure requires thermal reliability issues to be studied. To this end, simulation models were developed to study the robustness of QP. QP structures were fabricated, and thermal cycling tests were performed focusing on the reliability for various shapes of nodules, the basic physical interconnect unit of QP. Simulations were performed to determine stress over a range of temperatures and estimate low cycle fatigue lifetimes. Simulations considered two types of solder and several adhesives. Thermal cycling experiments indicate that QP provides a robust structure, in agreement with the simulation results.”
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Q. Zheng and G.H. Bernstein, “Quilt Packaging: Lining Up An Array of Opportunities,” featured case study, Olympus Microscop Newsletter 2012.

Abstract: “A new technology called Quilt Packaging (QP) shows great promise for boosting system-level IC package performance and lowering cost. A 2D system-in-package paradigm has been developed in the laboratory of Professor Gary H. Bernstein, Department of Electrical Engineering, Center for Nano Science and Technology, at the University of Notre Dame.”
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W.A. Zortman, D.C. Trotter, L.E. S. Rohwer, D. Chu, A.H. Hsia, G.Robertson, D. Greth, R. Jarecki, C.A. Sanchez, C.T. Derose, A.L. Starbuck, R.P. Timon, P.S. Davids, M.R. Watts, and A.L. Lentine. “Silicon Photonic Link in CMOS Quilt Package.” IEEE Avionics, Fiber-Optics and Photonics Digest CD, 2012.

Abstract: “A multifunction low-power, high-speed silicon photonic chip consisting of a resonant modulator and germanium detector is quilt packaged with CMOS receiver and driver electronics. Experimental data demonstrates this new route for intimate 2D-integration.”
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J.M. Kulick and G. H. Bernstein, “Quilt Packaging: A Revolutionary and Flexible Approach to High-Performance Systems in Package,” Advancing Microelectronics, 39(2), March/April 2012 (Featured Article)

Abstract: “Indiana Integrated Circuits (IIC), LLC offers an alternative solution known as ‘Quilt Packaging’ (QP) specifically for RF/microwave systems composed of different materials. QP is a direct edge-interconnect technology that has experimentally demonstrated less than 0.1 dB of insertion loss across the entire bandwidth ranging from 50 MHz to more than 100 GHz without any resonances. It enables multiple die from different materials and processing technologies to be integrated into a monolithic-like system that performs essentially as if it has been created as a single chip. It also has a significant potential in MEMS integration, power management, and large-format imaging array applications, with significant cost and performance advantages. It has evolved from a basic research concept into an integration solution ready for wider-spread adoption.”
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M.A. Khan A.M. Kriman, and G.H. Bernstein. “Thermal Modeling of Quilt Packaging Interconnects.” 2010 18th Biennial University/Government/Industry Micro/Nano Symposium, 2010.

Abstract: “This paper discusses thermal reliability simulations of Quilt Packaging (QP), a novel chip-to-chip interconnect technology. A simulation model of QP is developed. The issue of reliability arises due to the different coefficients of thermal expansion (CTE) of materials used in the QP system for the operating temperature of circuits. Thermal stress is produced due to the CTE differences, the magnitude of which depends on the materials and dimensions of the structure. Simulation results work as guideline to obtain reliability data for QP structures.”
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D. Kopp, M.A. Khan, S. Garvey, K. Anderson, J. Kulick, P. Fay, A.M. Kriman, and G.H. Bernstein, “Quilt Packaging: A Robust Coplanar Chip-to-Chip Interconnect Offering Very High Bandwidth,” Proc. 2010 International Conf. on Compound Semiconductor Manufacturing Technology (CS Mantech), p. 309, 2010

Abstract: “A novel coplanar waveguide-based chip-to-chip interconnect scheme called Quilt Packaging (QP) has been developed. This technology enables extremely high speed integration of multiple chips on Si substrates. The demonstration of this technology in GaAs and InP is ongoing. With this technology, wiring delays associated with signal transmission from chip to chip are greatly reduced. The mechanical properties of QP at elevated temperatures are under study to improve reliability.”
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K. Shenai, G.H. Bernstein, G. Xing, J. Wu, “Chip-scale DC/DC power converter,” Proc. Aerospace and Electronics Conf., NAECON, 2010.

Abstract: “The design of disruptive chip-scale integration of DC/DC power converters using breakthrough silicon and GaN power semiconductor switching devices, silicon CMOS control IC, MEMS inductor and microchip supercapacitor assembled using novel “Quilt Packaging” and microcooling to achieve nearly 90% power conversion efficiency is reported.”
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K. Shenai, “Heterogeneous Integration of DC-DC Power Converters,” Proc. IEEE International Conf. of Electron Devices and Solid State Circuits, EDSSC, 2010.

Abstract: “To achieve the highest power conversion efficiency, heterogeneous chip-scale integration of silicon-based and GaN-based power switches with SiC power diodes, silicon CMOS control IC, MEMS inductor and micro microchip supercapacitor assembled using advanced packaging and microcooling is reported.”
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W.L. Buckhannon, M. Niemier and G.H. Bernstein, “Bridging the HPC Processor-Memory Gap with Quilt Packaging,” Proc. Micro/Nano Symposium (UGIM), pp. 130-132, 2010.

Abstract: “High performance computing (HPC) systems are constrained in the areas of performance, power, and cooling. A new 2D technology, called “Quilt Packaging,” is presented as a possible solution to positively impact the processor-memory connection in these areas. A straw man architecture based on current HPC nodes in the RedStorm system at Sandia National Laboratories is used to explore the effects of Quilt Packaging on the connection between processor and memory.”
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D. Kopp, C. Liang, J. Kulick, M. Khan, G.H. Bernstein and P. Fay, “Quilt Packaging of RF Systems with Ultrawide Bandwidth,” Proc. of the IMAPS-Advanced Technology Workshop on RF and Microwave Packaging, San Diego, CA 2009.

Abstract: “Radio frequency (RF) performance of systems is significantly affected by the electrical properties and structure of the interconnect technology. Wire- and bump bonds to substrates can add inductance and capacitance that increase loss and latency, add resonances, and limit bandwidth, and approaches to mitigate these effects can increase power consumption. Chip stacking, in development is the silicon digital IC community, may ameliorate these effects for digital systems, but may not be suitable for RF analog circuits. Here, we present an alternative approach, called Quilt Packaging (QP), that is complementary to chip stacking, and is more relevant to the heterogeneous combinations of technologies that will be needed for advanced optical and RF systems. Quilt Packaging is a 2D approach that incorporates metallic features, or nodules, at the periphery of the dice to facilitate direct chip-to-chip interconnection. By connecting these nodules, which are as small as 10 microns wide (along the edge) and 20 microns deep (into the substrate), we form a quilt of chips touching at their edges that are interconnected with very wide bandwidths. The quilt of interconnected ICs is then placed into an electronic system, either in a package or on a board, in the same way that a individual conventional chip would be. We have demonstrated both theoretically and experimentally that the QP paradigm is capable of providing record-breaking RF performance in the plane of the ICs. We have previously reported measured insertion loss between Si ICs of 0.1 dB at 40 GHz. We will present simulations to 110 GHz showing projected losses as low as 0.05 dB at 110 GHz for optimized structures. Time domain measurements show delays as small as 2 ps between chips. We will also present frequency-domain measurements to 110 GHz that are currently in progress. We expect these results to highlight the promise of QP interconnects for RF system integration.”
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G.H. Bernstein, Q. Liu, M. Yan, Z. Sun, W. Porod, G. Snider and P. Fay, “Quilt Packaging: High Density, High-Speed Interchip Communications,” IEEE Trans. on Advanced Packaging, 30(4), 731-740, 2007 (TAP 2007 Paper of the Year)

Abstract: “Quilt Packaging (QP), a new superconnect paradigm for interchip communication, is presented. QP uses conducting nodules that protrude from the vertical facets of integrated circuits to effect a dense, fast, and reduced-power method of interfacing multiple die together within a package or on a multichip module. The concept of QP is presented along with a discussion of advantages over traditional system-on-chip and other system-in-package technologies. A process flow and results of chip fabrication are detailed. Simulations show expected signal propagation between adjacent die of greater than 200 GHz, and measurements of interconnected chips confirming low losses and resonance-free operation to at least 40 GHz have been achieved.”
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Q.Zheng, M.A. Khan, A.M. Kriman and G.H. Bernstein, “Electrical and Mechanical Performance of Quilt Packaging with Solder Paste by Pin Transfer,” to appear in Journal of Microelectronics Packaging.

Abstract: “Electrical and mechanical performance of quilt packaging (QP), a 2D system-in-package chip-to-chip interconnection, is presented. QP employs contacts at the edges of integrated circuit dice along their vertical surfaces. Based on 3D HFSS simulations, the self-inductance of QP can be less than 100 pH, and the self-capacitance can be less than 34 fF due to the shortness of the interconnection path. QP interconnection using solder paste with pin transfer is presented, and mechanical reliability is evaluated. A new pull test system specifically designed for QP is presented. The pull force that causes failure in a set of edge interconnects totaling 3 mm width of nodules is about 658 g-force for Sn63Pb37 and 953 g-force for SAC305.”
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Q. Liu, P. Fay and G.H. Bernstein, “A Novel Scheme for Wide Bandwidth Chip-to-Chip Communications,” Journal of Microelectronics and Electronics Packaging, 4(1), 1-7, 2007.

Abstract: “Quilt Packaging (QP), a novel chip-to-chip communication paradigm for system-in-package integration, is presented. By forming protruding metal nodules along the edges of the chips and interconnecting integrated circuits (ICs) through them, QP offers an approach to ameliorate the I/O speed bottleneck. A fabrication process that includes deep reactive ion etching, electroplating, and chemical-mechanical polishing is demonstrated. As a low-temperature process, it can be easily integrated into a standard IC fabrication process. Three-dimensional electromagnetic simulations of coplanar waveguide QP structures have been performed, and geometries intended to improve impedance matching at the interface between the on-chip interconnects and the chip-to-chip nodule structures were evaluated. Test chips with 100 µm wide nodules were fabricated on silicon substrates, and s-parameters of chip-to-chip interconnects were measured. The insertion loss of the chip-to-chip interconnects was as low as 0.2 dB at 40 GHz. Simulations of 20 µm wide QP structures suggest that the bandwidth of the inter-chip nodules is expected to be above 200 GHz.”
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G.H. Bernstein, Q. Liu, Z. Sun and P. Fay, “Quilt Packaging: A New Paradigm for System-in-Package,” Proc. IEEE 7th Electronics Packaging Technology Conf. (EPTC2005), pp. 1-6, 2005.

Abstract: “”Quilt packaging,” (QP) a new paradigm for interchip communication, is presented. QP uses conducting modules that protrude from the sides of integrated circuits to affect an enhanced-speed, reduced-power method of interfacing multiple die together within a package or on a multichip module. The concept of QP is introduced along with a discussion of advantages over traditional system-on-chip and system-in-package technologies. Details of a process flow and preliminary results are presented. Simulations show expected signal propagation between adjacent die of greater than 150 GHz”
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