Frequently Asked Questions

IIC develops and licenses semiconductor processing IP for ultra-high bandwidth, low-loss, reduced-power consumption and high- density interconnect applications to be used for heterogeneous system applications including Microwave/RF, Large Format Focal Plane Arrays, MEMs, Power, and high-performance computing applications. Quilt Packaging is compatible with standard fabrication tools and can be implemented into existing production lines using existing processing equipment.

All RF systems that employ multiple ICs suffer from some losses due to bandwidth constraints of interchip signal transmission. This problem is compounded by the requirement that a signal must tansmit from one chip, possibly through a package, to a substrate, and then back through the second package to the chip. All of these interfaces introduce loss and reflections. Quilt Packaging nearly eliminates power losses and reflections between chips by providing an ultra-short, direct chip-to-chip interface, and has been proven to provide bandwidth well in excess of 200 GHz.  In fact, we have shown that at 220 GHz, insertion loss due to the interchip QP technology is still well below 1 dB.

QP interconnections have been demonstrated at a density of 5 µm nodules on a 10 µm pitch, as fabricated in the Notre Dame Nanofabrication Facility. We anticipate that pitch as small as 6 µm is achievable for more-demanding applications.

Since QP interconnect structures, or nodules, are lithographically defined, they can be created in virtually any geometry desired. The nodule thickness is determined by the depth of the definition etch, and can be varied from as thin as 5-10 µm to as thick as 100s of µm for power applications.

Yes, QP provides unheard of design flexibility. By lithographically defining the nodule geometries, QP interconnections can be engineered so that fine-pitch digital bus bars, larger coplanar wave guides, and very large power/ground connections could all be placed on the same side of a single chip—no longer are designers limited to a one-size-fits-all wirebond or bump connection. Truly optimized system-in-package is now a reality!

One of the greatest advantages of Quilt Packaging is the possibility for true heterogeneous integration.  “Panels” in the “quilt” (i.e., chips in the quilted chip array) may now be optimized for processing, substrate material, cost, and many other factors.  For example, why use expensive chip real-estate for an inexpensive, low-tech antenna when you can quilt it to your expensive RF chip with no loss of performance at a fraction of the cost? The Quilt Packaging fabrication process is straightforward and allows for fabrication options in material systems including Si, GaAs, GaN (on Si or SiC), InP, and SiGe. Development work is underway to investigate QP for sapphire, glass, and ceramic.

QP is not intended to replace any existing packaging modality, but rather is complementary to wirebonding, bumping, and stacking. In fact, after two or more die are quilted, the quilt itself is treated as if it were a single chip (what we call a “metachip” or “quilt”) and placed in a package and wirebonded or bumped. Additionally, it is possible to combine QP and chip stacking to create entirely new system architectures.

Yes. Through an agreement with the University of Notre Dame, IIC has access to state-of-the-art fabrication, testing, and imaging facilities and equipment. IICs engineers are very experienced in R&D prototyping, process development,  and fabrication work, and are ready to partner with you for nanofabrication and development work needs.

IC offers a variety of licensing models that can be structured specifically to meet your company’s needs. Depending on the type of license, we can provide technology transfer support and very light scale manufacturing to help bridge the gap between development and production. Please contact us at information@indianaic.com or call us at (574) 217-4612.