Quilt Packaging Applications

Electrically, the QP interconnect performs as if it were an on-chip interconnect even though they run off-chip. Microwave measurements of preliminary test articles in Si-Si QP have demonstrated less than 0.1 dB insertion loss across the entire bandwidth from 50 MHz past 100 GHz, and preliminary GaAs-GaAs QP measured approximately 2 dB at 220 GHz. Preliminary GaAs and Si integration by QP measures under 1 dB from 50 MHz up to 220 Ghz. QP-enabled packaging improvements have the potential to significantly reduce the size, weight, and power requirements of QP-based MMIC technology, providing a flexible and cost-effective path to developing new high performance microwave systems.

Large format detector and projection arrays are becoming extremely expensive if not economically impossible to produce. QP enables tiling of arbitrarily large arrays from smaller, higher-yielding chips. QP offers benefits such as sub-micron chip-to-chip alignment accuracy and a better control of flatness across the entire array. Optimization of the dry etch process during fabrication can create very small and precise interconnect structures (with 10 micron pitch I/O on chip edge) and less than 10 micron chip-to-chip gap. This application can be implemented in materials including, but not limited to, Si, GaAs, and GaSb.

QP offers a revolutionary solution to power packaging problems. QP nodules can be fabricated in custom widths and depths, not only eclipsing the cross-sectional area of wire bonds, but at a fraction of the length of wire bonds, minimizing both resistance and inductance. As a significant added bonus, the power nodules are heat sinked to the substrate, so vastly more current can pass through nodules before risk of failure.

QP further offers the opportunity for new and exciting power electronic architectures. For example, modular chips, each with a fixed current-sourcing capability, could be quilted to easily and inexpensively assemble customized power systems.

The unique capability of Quilt Packaging to provide extemely accurate chip-to-chip alignment combined with the ability to integrate disparate materials is a major advantage in solid-state laser & waveguide integration. QP can be utilized to connect multiple waveguides on one chip to multiple waveguides on another chip (or chips) without the need for active alignment or additional complex, expensive, and space-consuming optics.

Benefits of this application include submicron chip-to-chip alignment for precision waveguide alignment and the ability to integrate disparate materials and/or process techonlogies monolithically. High coupling efficiency is achievable through QP engineered chip interfaces, with or without index-matching epoxy.

System size is paramount in many applications. In biomedical devices, system miniaturization means less pain for the patient, better monitoring and faster recovery times. Interposers are often employed to achieve high density devices, but suffer from high cost and difficulty managing the thermal issues for multi-material systems. Traditional silicon interposers also offer limited flexibility and their size is most often dictated by the size of the largest component.

Quilt Packaging allows interposers to be partitioned to each chip’s unique needs and geometry. This additional flexibility allows designers to eliminate every unnecessary bit of interconnect and packaging, achieving the smallest system design in an economically viable process.

With Quilt Packaging maufacturing processes, designers are no longer constrained to square and rectangular chips due to dicing saw limitations. QP can deliver hexagonally shaped chips or other geometries just as easily, optimized for a particular application. Also, hexagonal chips can more-efficiently use valuable optical stepper exposure field area to provide larger chip areas than what is available from square designs, with the added bonus of less wafer real estate wasted along the periphery.

Additionally, QP is not constrained to a 2D solution; the QP interconnect can be employed to enable orthogonally-oriented or curved chips for VCSEL or IMU systems.